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sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
TERASIC_AUDIO
- 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
image_control
- NIOSII通过IP核读取CMOS图像传感器在SDRAM中的数据-NIOSII read through the IP core in CMOS image sensor data in SDRAM
vga_ip_v1_00_a
- This simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.-This is simple VGA ip core sample. This was implemented in Spartan3A-1800 Kit.
cpu86
- CPU86 - Free VHDL CPU8088 IP core Copyright (C) 2005-2010 HT-LAB Quick run: 1) Open a DOSBox/Cygwin shell 2) Navigate to the web_cpu88/Modelsim directory. 3) Execute run.bat See website for more details. The CPU86 cor
pn2212
- Xilinx IP核DPD的产品说明，全英文文档，下载前需注意；-product notes of Xilinx ip core DPD
SOPC-based-boundary-scan-test-controller-IP-core-d
- 基于SOPC的边界扫描测试控制器IP核设计SOPC-based boundary scan test controller IP core design-SOPC-based boundary scan test controller IP core design
ethmac
- ethmac IP CORE VHDL IN QUARTUS-ethmac IP CORE VHDL IN QUARTUSII
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Embedesign
- 嵌入式ATA主机控制器IP核设计host controller -Embedded ATA host controller IP core design
How-to-adiet-a-ip-core
- 告诉你如何编写一个IP核，对于FPGA 的学习很有帮助-Tell you how to write a IP core, FPGA' s very helpful for
fpga-jianpan-ip-core
- 基于fpga的键盘设计ip核的vhdl源代码-Ip fpga design of the keyboard based on the vhdl source code for nuclear
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FP
vga-ip-core
- vga ip core 资料 说明如定制一个ip核-vga ip core information such as a custom ip core
FFT-module
- IP CORE ：FFT模块使用方法，内含源代码，希望对大家有帮助。-IP CORE: FFT module use, including source code, we want to help.